1. Field of the Invention
This invention relates to the process of manufacture of semiconductor devices which employ Shallow Trench Isolation (STI) and more particularly to use of negative photoresist and CMP for shallow trench isolation.
2. Description of Related Art
U.S. Pat. No. 5,350,486 of Huang for a "Semiconductor Planarization Process" shows a method of planarization using a photoresist (PR) layer to etch oxide from an oxide layer located over active areas. The method includes the steps of selectively etching portions of a glass structure that overlies portions of the oxide layer that have higher elevations than other portions of the oxide layer, and then etching the glass layer overall. The etching step includes forming a photoresist layer over the glass layer. A positive or negative photoresist layer is formed by exposing selected areas of the photoresist layer in areas over those portions of the oxide layer that have higher elevations than other portions of the oxide layer. As a result, the exposed areas of the photoresist layer are removed to form a set of windows therethrough thereby converting the photoresist layer into a photoresist layer. Then the glass layer is etched where it is exposed through those through the windows in photoresist layer. The master mask used in patterning the photoresist layer can be the same mask, or its negative, that is used in forming the metallization layer over which the oxide and glass layers have been formed. If the negative of the master mask is used then a positive photoresist layer is used. If the same master mask is used, then a reverse tone photoresist layer is used.
U.S. Pat. No. 5,691,215 of Dai et al. for "Method for Fabricating a Sub-Half Micron Device with Insulator Filled Shallow Trenches Planarized Via Use of Negative Photoresist and De-Focus Exposure" shows a process featuring smoothing the topography that exists after the insulator filling of narrow and shallow trenches, by creating photoresist plugs, only in the depressed topography regions. This is accomplished using a negative photoresist layer, a de-focus exposure, and the identical mask used to create the shallow trench pattern in a positive photoresist layer. A RIE (Reactive Ion Etching) procedure, with a 1:1 etching selectivity, is used to complete the planarization process. However, this patent does not show the invention's next CMP step.
U.S. Pat. No. 5,641,704 of Paoli et al. for "Method of Isolating Active Areas of a Semiconductor Substrate by Shallow Trenches and Narrow Trenches" teaches an isolation planarization using a negative mask before an etch back and CMP. However, Paloi teaches CMP but does not teach the Negative photoresist (PR) of the invention. See col. 5, lines 41-44.
U.S. Pat. No. 5,494,857 of Cooperman et al. for "Chemical Mechanical Planarization in Semiconductor Substrates" teaches an isolation planarization using a negative mask before an etch back and Chemical Mechanical Planarization (CMP).